The present invention relates to the field of electronics, and more specifically to the fabrication of single electron devices on a nanometer scale.
With single electron technology, the transport of individual electrons should be precisely controlled. By operating with fewer electrons than current electronic devices, single electron technology makes it possible to fabricate extremely small electronic structures that offer several advantages, such as increasing sensitivity and conserving power, as examples.
Although the potential benefit of single electron technology is clear, the fabrication and the reliable production of addressable structures and devices therefrom is in its infancy. This is because a single electron device is inherently of nanoscale order and no current technique has been developed to fabricate such nanoscale elements at the wafer level.
The core element for this technology is a single electron transistor (SET). SET is a nanoscale structure generally comprising a source, a drain, a gate, and a charging island (Coulomb island) separated from the source and drain by tunneling barriers. To date, the requirement for geometric control with nanometer scale precision has stalled development of devices comprising SETs. Additional fabrication issues have hindered the implementation of SETs. For example, for room temperature operation, the size of the charging island and the thickness of the tunneling barriers of an SET must be in the nanometer range. Typical geometrical constraints are that (a) the distance between the source and drain electrodes needs to be controlled so that the separation is in the nanometer range, and (b) the charging island (Coulomb island) must be precisely positioned between source and drain electrodes to allow electron tunneling via the charging island.
To meet the above requirements, several techniques have been investigated, including e-beam lithography, the creation of gaps between two electrodes using electromigration, oxidation of metal film using scanning tunneling microscope (STM), and tailoring the gap of the two electrodes through electrochemical deposition. Unfortunately, none of these techniques have been able to consistently control the gap between the source and drain electrodes at the wafer level. For positioning charging islands between source and drain electrodes (constraint b), additional methods have been explored, including applying nanoparticles on predefined source and drain electrodes, creating nanoscale grains between source and drain electrodes without precise positioning control, using STM to define charging islands and tunneling barriers, or using AFM (atomic force microscopy) to create charging islands and tunneling barriers by applying mechanical force or voltage pulses. Unfortunately, these techniques are unable to precisely control the positioning of charging islands and when scanning probes are used, the techniques are too slow for practical application. The limitations have lead to the current inability to practically fabricate real and useful SETs at the wafer level.
As such, there remains a need for the fabrication of a usable single electron structure that is also practical, efficient, and economical and capable of being used for single electron devices. The fabrication technique should reliably control tunneling gaps between source and drain electrodes and provide for exact positioning of charging (Coulomb) islands as well as operate at room temperature.